Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.
Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads
## Episode Summary
In this episode, we cover:
- **Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads** (arXiv)
- **HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference** (arXiv)
- **Efinix Sapphire RV64 SoC – Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs - CNX Software** (google_riscv)
- **Efinix Goes 64-Bit with Its Latest Sapphire SoC FPGA Cores, Based on the RISC-V Architecture - Hackster.io** (google_riscv)
- **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv)
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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
25 Oct 2026
panvram: GPU-resident random access to a human pangenome cohort
## Episode Summary
In this episode, we cover:
- **panvram: GPU-resident random access to a human pangenome cohort** (arXiv)
- **BS-Spec: BFP-Based Bit-Sharing for Self-Speculative LLM Decoding with LUT-Driven Mixed-Precision Acceleration** (arXiv)
- **Nuvia Architects’ New CPU Core Can Use Arm, RISC-V or x86 - HWCooling.net** (google_riscv)
- **Lanxin Computing Unveils RISC-V Supernode Built on Its 48-Core LX500 Inference Chip - Pandaily** (google_riscv)
- **Upbeat Technology’s Bluemag Pi Pairs RISC-V Processors and AI Inference for Advanced Flight Control - Embedded Computing Design** (google_riscv)
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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
24 Oct 2026
Proba: A High-Performance, Low-Traffic Probabilistic Spatial Memory Streaming Prefetcher
## Episode Summary
In this episode, we cover:
- **Proba: A High-Performance, Low-Traffic Probabilistic Spatial Memory Streaming Prefetcher** (arXiv)
- **Stop Paying by the Letter: Accelerating Full-Chip RTL Simulation with Host-Side Tokenized Logging** (arXiv)
- **UltraRISC Shows UR-CP400 RISC-V Core IP: RVA23, 8-Wide Out-of-Order, Delivery in Q1 2027 - Pandaily** (google_riscv)
- **SpacemiT Pairs V100 RISC-V Server CPU With Three Servers, Kunlunxin M100 Validation and Linux - Pandaily** (google_riscv)
- **RISC-V data center processors: server requirements - NeoTeo** (google_riscv)
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*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
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