EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast.
Industry Briefings:
Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co.
Focus Deep Dives:
Unpack physics, plasma, optics and how EUV scanners really work.
Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites.
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New TSMC and Samsung figures reinforce the scale of semiconductor demand, while GlobalFoundries adds a dated interposer-supply plan for TSMC. The focus examines the Hyper-NA study's principal unresolved constraint: a smaller focus budget and the need for thinner resists. Architectural reuse could limit transition spending, but the proposed optics are not a commercial production commitment.
Key takeaways
- TSMC reported September revenue of NT$511.86 billion, up 54.6% year on year and down 0.6% month on month; January–September revenue grew 41.1%.
- Samsung's preliminary Q3 guidance projects KRW195 trillion in consolidated sales and KRW107.4 trillion in operating profit, versus KRW12.17 trillion profit a year earlier; these are estimates, not final or foundry-specific results.
- SIA reported sales exceeding US$1 trillion through August; its August figure of US$159.7 billion, up 8% sequentially, uses a WSTS three-month moving average.
- Reuters reported AMD's plan for a substantial 2027 supply increase and need for more advanced wafer capacity; no wafer-volume, node-allocation or new-fab commitment was disclosed in those comments.
- GlobalFoundries announced a US$2 billion agreement with TSMC for CoWoS silicon interposers, an initial five-year term and an expected Malta, New York volume ramp in H1 2028; this is packaging-component capacity.
- The October 1 Hyper-NA paper proposes at least 0.75 numerical aperture at 13.5 nm and approximately 5 nm optical half-pitch; its roughly ten-year development estimate is not a committed delivery date.
- The study identifies an approximately halved idealized depth of focus versus 0.55 NA, motivating better focus control and thinner resists; actual process windows remain pattern-dependent.
- Source reuse leaves future power needs open; polarization can improve contrast but introduces a photon penalty, and a proposed 0.75-NA micro-exposure tool could support resist development.
- ASML and TSMC have Q3 results scheduled for October 14 and 15 respectively; watch output guidance, advanced-node capacity and packaging execution, alongside measured Hyper-NA resist/focus results.
Glossary
EUV — Extreme ultraviolet lithography; the proposal retains the 13.5 nm wavelength.
High-NA — High numerical aperture EUV; the 0.55-NA platform used as the study's comparison.
Hyper-NA — Proposed EUV architecture with numerical aperture of at least 0.75.
Half-pitch — Half the repeat distance of a periodic pattern; distinct from a commercial node name.
Depth of focus — Axial imaging tolerance; an idealized optical value is not a complete manufacturing process window.
Resist — Photosensitive patterning film; thinning it changes photon absorption and pattern-transfer requirements.
Edge-placement error — Difference between an intended pattern edge and its realized position.
Micro-exposure tool — Small-field research exposure system for developing materials under future optical conditions.
CoWoS — Chip on Wafer on Substrate, TSMC's advanced packaging platform.
5 Oct 2026
[066] Industry briefing - EUV The Focal Point
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Micron's September 30 results provide a concrete follow-up to last week's investment outlook, while Samsung projects a larger share of DRAM wafer capacity going to HBM. This episode examines how take-or-pay commitments improve investment visibility and why product mix, qualification and delivery timing still determine the EUV implications.
Key takeaways
- Micron reported fiscal Q4 2026 revenue of $54.23 billion and full-year net capital expenditure of $27.37 billion; financial growth is not a physical capacity measure.
- Micron guides approximately $25 billion of net capex for the first half of fiscal 2027, with higher spending in the second half; $25 billion is not its full-year budget.
- Samsung's Kim Taewoo expects HBM to use nearly 30% of industry DRAM wafer capacity in 2027, versus about 20% currently; this is an expectation, not market share or bit share.
- Micron reports 26 multi-year take-or-pay SCAs, estimated to cover over 35% of revenue through 2030, with some agreements extending into 2031.
- Micron identifies 1-gamma as its largest DRAM production node; its technology documentation confirms EUV use.
- Micron says Singapore HBM packaging cleanroom preparation is ahead of plan, with initial output expected in early calendar 2027; packaging is distinct from front-end wafer capacity.
- The September 28 outlook is partly answered on spending; a precise Micron HBM4E production date remains unestablished in the sources used here.
- Analysis: translating contracted bits into exposure demand requires product mix, bits per wafer, yield and patterning-flow assumptions.
- Fresh qualifying news was concentrated in memory; already-covered A14 pilot and silicon-wafer pricing reports were excluded from the news segment.
Glossary
EUV — Extreme ultraviolet lithography, used to pattern selected critical semiconductor layers.
HBM — High Bandwidth Memory, a stacked DRAM product designed for high data bandwidth.
DRAM — Dynamic Random-Access Memory, volatile memory used in computing systems.
SCA — Strategic Customer Agreement; Micron uses this term for its multi-year customer supply arrangements.
Take-or-pay — A contractual obligation to take an agreed quantity or make the required payment, subject to the agreement's terms.
Net capex — Capital expenditure after the relevant offsets; Micron's guidance is net of anticipated government incentives.
1-gamma — Micron's EUV-enabled DRAM technology generation, also written 1γ.
Front-end capacity — Wafer fabrication capacity, distinct from subsequent packaging and assembly.
Qualification — Validation that a product or manufacturing process meets the relevant requirements before broader deployment.
28 Sept 2026
[065] Industry briefing - EUV The Focal Point
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TSMC’s A14 program is becoming more operational: reported pilot timing is moving earlier while the design ecosystem is filling in with certified flows, interface IP and customer test-chip activity. At the same time, reported 300-millimeter wafer price pressure shows that AI-driven scarcity is moving deeper into the manufacturing supply chain. The EUV implication is important: more near-term pressure on the established EUV fleet does not mean TSMC is bringing High-NA production forward.
Key takeaways
- TrendForce reports that TSMC could begin A14 pilot production at Baoshan in 1Q27, while the company’s volume-production target remains 2028.
- Cadence and Synopsys announced certified EDA flows for TSMC A14 at the 2026 North America OIP Ecosystem Forum.
- Cadence says UCIe-64G IP has taped out on A14, adding a concrete interface-IP milestone to the node’s design ecosystem.
- Analog Bits says its IP will be included in an upcoming customer test-chip tapeout on TSMC A14.
- Siemens and TSMC are highlighting AI-assisted automated DRC fixing as a way to reduce manual design iterations and accelerate time to tapeout.
- TrendForce reports that 2027 long-term agreement prices for 12-inch wafers could rise roughly 15–25% for epitaxial wafers and more than 40% for polished wafers.
- The reported A14 pilot acceleration does not change TSMC’s recently stated 2030 start for High-NA EUV high-volume manufacturing.
- No new ASML scanner shipment count was disclosed this week; the strongest EUV signals came from A14 readiness and upstream wafer supply.
Glossary
Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for the most demanding patterning layers in advanced logic and memory.
High Numerical Aperture (High-NA) EUV — ASML’s next-generation EUV platform with higher numerical aperture for tighter single-exposure patterning.
A14 — TSMC’s advanced logic process generation scheduled for volume production in 2028.
Electronic Design Automation (EDA) — Software tools used to design, verify, implement and sign off integrated circuits.
Design Rule Check (DRC) — Verification that a chip layout complies with foundry manufacturing rules.
Tapeout — The point at which a chip design is finalized for mask generation and fabrication.
Long-Term Agreement (LTA) — A multi-period commercial contract used to secure supply, pricing or both.
300-millimeter wafer — The standard silicon substrate diameter used for most advanced semiconductor manufacturing.
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