Wearing Flip-Flops

About Wearing Flip-Flops

In the world of semiconductor engineering, the path from architecture to silicon is rarely a straight line. Wearing Flip-Flops (https://wearing-flip-flops.com/) is a podcast dedicated to the people that love hardware, engineers, architects, and leaders navigating the challenges of modern SOC (System-on-Chip) verification. Hosted by industry veteran Ronen Laviv, the show strips away the corporate jargon to have honest, high-level technical conversations about EDA tools, simulation platforms, and the verification bottlenecks that keep R&D teams up at night. Whether we’re discussing the latest in hardware-assisted verification or the unique culture of lean startup teams, we keep it grounded, insightful, and true to our name completely informal. If you’re looking for a technical deep dive without the stiff suit-and-tie atmosphere, grab your flip-flops and join us. (https://wearing-flip-flops.com/)

Publisher

Wearing Flip-Flops

Category

technology

Language

en

Explicit

No

First episode

9 Apr 2026

Latest episode

19 Oct 2026

Latest episodes

13 episodes in the feed.

1. 

   19 Oct 2026

   Who Signs The Tapeout ?

   When an AI agent designs and verifies the chip, and a human signs the tapeout, who owns the bug that reaches silicon? Prof. Ziyad Hanna, Corporate Vice President of R&D and Strategic Head of AI at Cadence Design Systems, joins Ronen Laviv to talk about generative AI and agentic AI in chip design. Ziyad spent decades in formal verification at Intel and Cadence before taking on AI strategy across Cadence's EDA platforms. In this episode: - The role of EDA companies in generative AI: model provider, orchestration layer or ground truth? - Level-5 autonomy for the Cadence ChipStack AI Super Agent, and why AI in front-end design and verification is still early - What sits inside the claim of 40x faster RTL validation - Why Cadence bought ChipStack instead of building it - How a head agent coordinates design and verification agents, and where it hands back to the engineer - Accountability when an AI agent's work fails in silicon - Multi-vendor EDA flows: does agentic AI make them harder? - When chip companies should build their own AI agents, and when to buy - Which EDA products generative AI could replace, and how chip designers can prepare This is part 1 of 2 with Ziyad Hanna. Part 2, "Probably Proven", covers formal verification, AI and cloud. Episode article, key takeaways and transcript: https://wearing-flip-flops.com/who-signs-the-tapeout (https://wearing-flip-flops.com/who-signs-the-tapeout/) Wearing Flip-Flops is a hardware podcast for chip designers, with deep dives into verification, emulation and the silicon powering AI. https://wearing-flip-flops.com (https://wearing-flip-flops.com)

2. 

   5 Oct 2026

   The Tools, The Bill, and the jobs

   An AI agent built a complete RISC-V core in 12 hours. So why can't it tape out your SoC yet? Tzviel Lemberger from Google is back to separate the breakthrough from the hype. Description Tzviel Lemberger leads AI activities in Google's Silicon Hardware group, and he's back for round two. Last time we ran out of time with questions still on the table. This time we went straight at them. Tzviel compares today's AI chip design demos to the first four-minute mile. Once one runner broke the barrier, everyone believed it was possible. A RISC-V core in 12 hours does the same thing for chip design. Then reality shows up: a full SoC with dozens of IPs, legacy layout, PPA tradeoffs, and a spec that changes every week is a different race altogether. We talk about what chip designers should expect from EDA vendors now that agents, not humans, run the tools. An agent can generate a million versions of an RTL block. If every evaluation needs an overnight run, the flow never converges, either on time or on budget. We also cover why multi-vendor AI flows are stuck on data formats, and how agents move work from engineers to compute. Tzviel explains what owning the entire stack, from models to cloud to silicon, means for co-design at Google. Then we get practical. Is RTL the new assembly language? Will lint and log-crawling be handed to agents? Will waveform viewers and formal engines survive as independent checks? And the question everyone keeps asking: if AI does the junior-level work, how do juniors become senior architects? If you work in RTL design, verification, physical design, or EDA, and you want a grounded view of where AI chip design really stands, this one is for you. In this episode The four-minute mile of chip design: what AI demos prove, and what they don't Agent-friendly EDA: faster, lighter feedback loops for AI-driven flows Multi-vendor AI flows and the data format problem From human work to compute work Is RTL the new assembly? Higher-level hardware languages The junior-to-senior gap in the AI era How engineers can prepare to what's coming Enjoyed it? Rate and review Wearing Flip-Flops. It's the single biggest thing that helps other chip designers find the show. Have a topic worth an episode, or want to be a guest? drop us a note.

3. 

   23 Sept 2026

   Googler in Flip-Flops

   Why do AI chip-design demos look amazing and then stall before production? Tzviel Lemberger, who leads AI activities in Google's Silicon Hardware group, has seen enough of them to draw a hard line. "90% accurate" in an EDA flow isn't a win. It's a respin. Tzviel brings about 16 years across Marvell, Intel, and Google. In this episode he covers: Turning every engineer into an agent developer while central teams build the moonshots Why design intent needs to leave engineers' heads so AI can actually use it Partnering in the AI era: working with EDA vendors, startups, and domain experts AlphaChip and an example case for skipping the LLM using different AI for chip design tasks Who owns the bug when AI writes the RTL and the silicon comes back broken The open problem: when agents write and run the tests, who's the independent check? Tzviel ends with a question he thinks about daily, so bring your answer. Enjoyed it? Rate and review Wearing Flip-Flops, and share it with a chip design or verification engineer who'd appreciate it. Have a topic worth an episode, or want to be a guest? Ping us on Linkedin. Hosted by Ronen Laviv. Full episode page: wearing-flip-flops.com

4. 

   9 Sept 2026

   The Death Of The Waveform Viewer

   Nobody enjoys opening a waveform viewer at 11pm. So here's the question this episode starts with: if AI reads the simulation database directly and does the root cause analysis for you, how much time are you actually spending in waves a year from now? Predrag Nikolic, AI Tech Lead at Veriest, thinks a lot less, and he is careful to say he hopes so rather than knows so. The logic is worth following. A waveform viewer is a human debug interface. It exists because a person has to eyeball signals to work out why a test failed. AI does not need pictures, it works against the database, and root cause analysis on failing regressions is already one of the few places generative AI genuinely earns its keep in verification today. Extend that and manual waveform browsing becomes the fallback rather than the first move. The obvious counterargument is that you open waves precisely when you do not trust what the tool just told you. That is exactly where the rest of the conversation goes. Veriest works hands-on inside customer verification teams across many companies, so this is the pattern Predrag sees across a lot of SoC verification flows rather than one company's experience. Yours probably looks different in places, and that is the interesting part. Also in this episode: Closed-loop verification, where AI debugs a failure, proposes a fix and re-runs the regression, exists at most serious shops now. Almost nobody runs it day to day. Predrag's read is that the gap is adoption and efficiency, not capability. Why design verification stays in SystemVerilog and UVM even though LLMs write better Python. There is far more Python in the training data, so the models are better at it, but a human reviews every line and that human is a verification engineer who knows SV. The reviewer is the constraint, not the model. Why the next wave of AI lands on the passive side of the testbench, monitors, checkers, coverage inspection and documentation, before it touches sequence and test generation. Build vs buy for AI verification infrastructure, from someone sitting inside customer teams while they make the decision. What EDA vendors have to deliver before any of this is trusted in a signoff flow. And the bottleneck waiting on the other side of all of it: simulation runtime. Disagree? Good. Tell us where your verification flow looks different. Wearing Flip-Flops is a podcast about hardware and chip design, hosted by Ronen Laviv. Deep dives into verification, EDA, silicon architecture and the engineering behind the AI hardware buildout, for the people who actually design the chips. All episodes: https://wearing-flip-flops.com (https://wearing-flip-flops.com) #chipdesign #verification #systemverilog #uvm #eda #semiconductors #asic #functionalverification #waveformviewer #rtl

5. 

   3 Aug 2026

   Who owns the AI chip design stack?

   Joining us for a post-DAC debrief, Sirish (CTO of (http://mooreslab.ai)Mooreslab.ai (http://Mooreslab.ai)) breaks down the evolving role of AI in chip design. We explore who controls the AI chip design stack, how big EDA vendors leverage their platform advantage, and what the future holds as AI continues to reshape the industry.

6. 

   21 Jul 2026

   AI in verification, build vs buy

   In episode 8 we host Sirish Kumar Munipalli, Co-Founder and CTO of MooresLabAI, an AI company building agentic automation for chip design verification and debug. What we cover: Build vs buy for AI verification tooling: when it makes sense for a DV team to build its own agents, and when that turns into a second product you never wanted to maintain. Where AI actually earns its place today in functional verification and debug, versus where it's still demo-ware.

7. 

   6 Jul 2026

   Emulation in Flip Flops (Part 2)

   Simulation runtime stops scaling long before your gate count does. Somewhere past a few hundred million gates, the weekend regression becomes the critical path, and the decision to move to emulation stops being academic. In this episode we host Frank Schirrmeister, Executive Director of Strategic Programs, System Solutions at Synopsys, who has worked across emulation and hardware-assisted verification for most of his career. What we cover: The real decision boundary between simulation, emulation, and FPGA prototyping, and the workloads where each one is the wrong tool. Where emulation earns its cost: long software-driven tests, full-SoC scenarios, power and performance analysis, and pre-silicon software bring-up. And where teams burn capacity on jobs that belonged in simulation. AI in emulation. Trends review. How startups and large enterprises use emulation slight differently. How AI and large accelerator designs are pushing runtime, capacity, and debug visibility, and what that does to a verification plan. Where Frank sees emulation heading, and what's hype versus what's actually changing in the flow. This is Part 2 of the conversation. Useful if you run verification, plan compute for it, or want a clearer mental model of when hardware-assisted verification is worth it.

8. 

   22 Jun 2026

   Emulation in Flip Flops (Part 1)

   Simulation runtime stops scaling long before your gate count does. Somewhere past a few hundred million gates, the weekend regression becomes the critical path, and the decision to move to emulation stops being academic. In this episode we host Frank Schirrmeister, Executive Director of Strategic Programs, System Solutions at Synopsys, who has worked across emulation and hardware-assisted verification for most of his career. What we cover: The real decision boundary between simulation, emulation, and FPGA prototyping, and the workloads where each one is the wrong tool. Where emulation earns its cost: long software-driven tests, full-SoC scenarios, power and performance analysis, and pre-silicon software bring-up. And where teams burn capacity on jobs that belonged in simulation. Trends review. How startups and large enterprises use emulation slight differently. How AI and large accelerator designs are pushing runtime, capacity, and debug visibility, and what that does to a verification plan. Where Frank sees emulation heading, and what's hype versus what's actually changing in the flow. This is Part 1 of the conversation. Useful if you run verification, plan compute for it, or want a clearer mental model of when hardware-assisted verification is worth it.

9. 

   8 Jun 2026

   Silicon Valley, Taiwan Alley

   Where the chip supply chain quietly breaks: the Taiwan question, espionage that needs no invasion, and a single dutch point of failure.

10. 

    25 May 2026

    The Winner Loses

    Are we paying a massive "productivity tax" on today’s complex SOC verification just because the industry chose UVM over Specman ? Look down at your keyboard. The only reason it starts with Q-W-E-R-T-Y is because 19th-century mechanical typewriters would jam if typists went too fast. It was literally designed to slow you down. The Dvorak keyboard layout was demonstrably faster and more ergonomic, yet QWERTY completely dominates the world. What on earth does a 150-year-old keyboard layout have to do with modern semiconductor verification? Everything! In this episode of Wearing Flip-Flops, we expose how Specman (E) lost the market-share war to UVM (SystemVerilog), despite being a fundamentally superior, more productive verification language. Our guest is Chico, was the VP of R&D at Verisity (the creators of Specman that was acquired by Cadence), an Intel Fellow who managed massive global migrations from Specman to UVM, and today contributing to the verification world at Nvidia. We'll also cover: The Quantifiable Productivity Premium: Chico breaks down the exact data. How much faster can engineering actually verify a complex project in Specman compared to SystemVerilog? (The gap is bigger than you think). The Code & Debugging Overhead: Why are modern verification teams writing massive amounts of boilerplate code just to do what Specman handles natively? Chico compares the true cost of maintaining and debugging both environments. The Great Migration Hangover: What happens under the hood when a tech giant decides to switch from Specman to UVM? Chico shares the hidden architectural bottlenecks, engineering friction, and retraining hurdles that never make it into the manager's slide deck. Are We Trapped? If Specman is objectively more productive, why did the industry standardize on UVM? Find out the corporate alliances and industry chess moves that locked verification engineers into the "QWERTY keyboard" of chip design. Hit play to hear Chico strip away the marketing fluff and give a raw, honest look at the code, the politics, and the engineering reality.

11. 

    11 May 2026

    The Hyperscale Playbook - Part 2

    We’re jumping back in for part two of the SOC Hyperscale playbook with Claudio to see how 26 years of experience at Amazon translates to the high-stakes world of silicon verification. While our last chapter laid the groundwork for scaling, this session gets into the "make or break" decisions that every manager eventually faces in the trenches. We transition from broad strategy to the gritty reality of the lab, where Claudio helps us navigate the fine line between efficient engineering and the technical debt that can sink a project. In this chapter, we tackle the big questions every verification lead is asking: The Reusability Debate: Is it always worth the effort for a team to focus on a massive, reusable test environment, or are there times when "quick and dirty" actually wins? The AI Reality Check: We cut through the marketing noise to find out: is AI truly ready to fully debug failing tests, or is the "magic button" still a myth? Timing the Shift-Left: When is the exact moment you should start running emulation tests to ensure your schedule doesn't fall apart during the final stretch? The Industry’s Biggest Hurdle: What is the absolute #1 pain point for verification right now that even the giants like Amazon have to wrestle with? This session serves as a tactical survival guide, turning decades of experience into actionable insights for anyone navigating the complexities of modern, large-scale hardware development. So, leave the corporate boots at the door, kick back, and put on your flip flops, it's time to dive into the episode

12. 

    28 Apr 2026

    The Hyperscale Playbook - Part 1

    Chip design verification isn't just about finding bugs, it's about managing massive-scale risk. Today, we’re hosting Claudio, Verification Manager for Amazon’s Graviton team, to discuss the reality of verifying hyperscale silicon. We’re cutting through the noise to answer the core questions: What actually makes a 'good' verification plan? How do you know when you’re truly ready to tapeout? And how do you handle verification when the stakes are as high as a global cloud provider? Join us as we explore the engineering realities of high-stakes silicon design

13. 

    9 Apr 2026

    Introduction - Hitting the Verification Wall

    In this first episode, meet the hosts and dive into one of the biggest problems that the hardware industry is facing

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