00:00 Andrew Zonenberg Introduction
01:48 Where did your interest in HW security come from?
04:12 What’s the difference between FPGA & ASIC development?
05:45 FPGA experience
06:00 UNIX style OS for PICs
08:35 PCB checklist https://github.com/azonenberg/pcb-checklist
09:35 What's your motivation for your work on high speed electronics
11:17 One goal of Andrew’s is to replace some Cisco switches with his own design
12:12 Where are the challenges in building a high speed switch like this?
13:52 How do you get something like this to work first time?
15:40 Sonnet for simulation https://www.sonnetsoftware.com/
16:55 OpenEMS https://openems.de/start/
18:08 Is it possible to build an intuition for high speed layout?
20:43 New lab toys
24:22 Andrew’s work on scope probes
25:12 Signal path review of AKL-PT1 https://www.youtube.com/watch?v=eZhMIR0l3xU
26:30 Buy a probe from Elegant Invention: https://shop.elegantinvention.com/collections/antikernel-labs
27:00 AKL-PT2 - solder on version
29:05 What’s the cheapest bit of kit for signal integrity
30:45 Tips on 2nd hand tools
33:12 Andrew’s preference is equipment that is no longer manufactured but still in support
35:00 Sampling scope for repetitive signals - eye diagrams
35:40 Ted Yapo’s super con talk on sampling scopes: https://www.youtube.com/watch?v=99u53V7uDFY
36:54 Sampling scopes could be cheaper solution for entry level signal integrity
37:08 Freesample: https://github.com/azonenberg/freesample
38:30 Explanation of how a sampling scope works
41:47 glscopeclient: https://github.com/azonenberg/scopehal-apps
45:35 glscopeclient roadmap
50:30 probono or discounted services for open hardware projects
53:09 contacting Andrew https://twitter.com/azonenberg
31 Mar 2021
Piotr Esden-Tempski
00:00 Introducing Esden
00:58 Unnamed RE podcast https://unnamedre.com/episode/44
01:43 top level overview of the Glasgow board
03:51 FPGA tools integrated into Glasgow tools
06:20 USB speed optimisation
06:30 Talk by Attie Grande https://fosdem.org/2021/schedule/event/glasgow/
08:03 Comments in Glasgow code
09:03 Update on Glasgow Crowd Supply
10:15 Shortage of ICs, impacting Blackmagic Probe
12:07 Having to place orders for Glasgow from manufacturers
13:42 iCEBreaker FPGA board
18:50 Piggybacked RAM
19:29 Doom on iCE40 by Sylvain Munaut
21:00 Underestimating possibilities of small FPGAs
24:56 What role do the Open Source EDA tools play in your business
29:30 Brief history of 1 Bit Squared
32:01 Black Magic Probe still supported?
37:57 1 Bit Squared expanding
38:10 Esden’s thoughts on community
41:51 Work by Sophi Kravitz and others on Hackaday Supercon
42:42 Adafruit community
43:30 Common problem is too much leeway, being afraid to say stop
45:05 Human stuff is part of technical stuff
Follow Piotr on twitter here: https://twitter.com/esden
15 Mar 2021
Al Wood
00:00 Introducing Al
01:26 Discovering Yosys
02:51 Lattice hx8k
04:58 OSHUG
05:47 The Coal Hole
06:15 OSHcamp workshop
06:55 Blackice memory & co-processor
07:34 FTDI tax
11:30 Raspberry Pi as programmer
13:50 HX4K with Yosys
15:00 sram chip - retro computing
16:10 Mystorm Forum
18:34 BBC Atom & Micro
20:13 What would you do to get more people interested in FPGAs
22:49 Verilog is a double edged sword
23:04 Higher level HDLs - nMigen
27:27 nMigen has built in support for Formal Verification
27:50 Glasgow & nMigen
28:40 nMigen support on myStorm boards
29:14 what’s been the impact of OSS on your professional and personal life
29:45 XMOS
31:05 Transputer
34:37 Interrupts are bad
37:00 building your own processors in FPGAs
38:49 where do you see FPGA tools in 5 years
43:02 Raspberry Pi RP2040 PIOs
48:30 New FPGA architectures
49:20 How to get in touch with Al
40:31 Streams on a Wednesday 8pm GMT http://twitch.tv/folknology
50:20 ecp5 based FPGA myStorm board incoming
15 Mar 2021
Olof Kindgren
00:00 Introducing Olof Kindgren
01:03 FOSSi
02:34 ORConf
04:41 FOSSi Dial-Up: https://www.fossi-foundation.org/dial-up/
06:20 75% of people who taped-out were software engineers
06:40 LibreCores
08:30 LibreCores vs OpenCores
09:31 Community building
10:53 SERV - an award winning RISC V processor
12:33 What is a bit serial core
13:43 Creativity award
14:02 CORE SCORE!
15:45 Corey
18:14 Olof doesn’t have enough FPGA boards
18:41 Documentation week
19:20 SERV documentation
20:06 How is Open Source shaping the EDA world
22:12 Engineering time is expensive
23:28 Fixing bugs in Open Source toolchains
25:25 no Formal Verification tools
26:17 GHDL
26:34 Yosys is an amazing synthesis tool
28:15 Bridging between proprietary and Open Source tools
28:35 Cocotb
29:48 Presenting the best interviewee award
Follow Olof on twitter: https://twitter.com/OlofKindgren
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